ISP RTL Design Manager

Role Overview

This role leads the architecture and RTL implementation of ISP (Image Signal Processing) hardware solutions, translating complex ISP algorithms into efficient hardware designs. The position combines deep technical expertise in digital design with team leadership responsibilities, driving cross-functional collaboration to deliver high-performance, low-power ISP solutions.

Key Responsibilities

• Implement ISP algorithms into hardware using Verilog, SystemVerilog, and/or SystemC (HLS).

• Define ISP hardware architecture aligned with product features, performance targets, gate count, and power constraints.

• Perform logic verification at ISP and system levels.

• Optimize RTL design for reduced gate count and lower power consumption.

• Collaborate closely with algorithm teams, digital system teams, and cross-site design leaders.

• Lead, mentor, and supervise a team of RTL design engineers.

• Drive project execution to ensure timely and high-quality deliverables.

Ideal Requirements

• MSEE, BSEE, or equivalent with 7+ years of digital design and verification experience.

• At least 3 years of project or people management experience.

• Strong experience in CMOS Image Sensors and ISP architecture.

• Proficiency in SystemC/C++, SystemVerilog, and Catapult HLS tools.

If you would like to be considered for this opportunity, please forward a copy of your full CV to melissa.lin@ambition.com.sg

Data provided is for recruitment purposes only. Only shortlisted candidates will be notified.

Business Registration Number : 200611680D | Licence Number : 10C5117 | EA Registration Number: R25127614