Principal Design Engineer

What You'll Do

• Use Synopsys/Cadence tools to synthesize designs from RTL to netlist.
• Create timing constraints for functional and test modes, working closely with design and DFT teams.
• Perform Static Timing Analysis (STA) and achieve timing closure.
• Write low-power intent files (CPF/UPF) and verify them using CLP/VCLP.
• Run logic equivalence checks to ensure correctness.
• Collaborate with physical design engineers to fix netlist and timing issues.

What We're Looking For

• Degree in Electrical/Electronic Engineering (Bachelor's or Master's).
• Hands-on experience with Synopsys or Cadence tool suites.
• Strong TCL scripting skills: Python is a plus.
• Team player with the ability to work independently and meet deadlines.
• Good communication skills (written and verbal).